During the design of circuits, many different devices are connected together in multiple ways. Internal paths critical to the operation of circuits such as memory should be analyzed for design and timing margins. Without such analysis, robust designs are more difficult to achieve.
In particular, the issue arises for analysis and verification of third party circuits where the detailed design information such as schematics are not available. Current methods for analysis of circuits may rely on transistor level simulation of the circuit, however this may be complicated and time consuming.
Accordingly, what is needed is more efficient and less time-consuming method for tracing paths within a circuit. The present invention addresses such a need.